Architecture of a FPGA-based Coprocessor: the PAR-1

J. Moran, E. Juárez, S. Alexandres, J. Meneses

IEEE Symposium on FPGA's for Custom Computing Machines - FCCM '95, Napa (United States of America). 19-21 April 1995

Summary:

The implementation of a FPGA based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural improvements for general FPGA based computing machines.

Keywords: Coprocessors , Field programmable gate arrays , Delta modulation , Application software , Prototypes , Circuits , Hardware , Software prototyping , Logic programming , Master-slave

DOI: https://doi.org/10.1109/FPGA.1995.477405

Publication date: 1995-04-19.

Citation:
J. Moran, E. Juárez, S. Alexandres, J. Meneses, Architecture of a FPGA-based Coprocessor: the PAR-1, IEEE Symposium on FPGA's for Custom Computing Machines - FCCM '95, Napa (United States of America). 19-21 April 1995.